1. Technical Field
The disclosure relates generally to the field of hardware configuration within the context of an interconnect bus. In one exemplary aspect, the disclosure is directed to methods and apparatus for switching between dedicated hardware configurations for a device on an Inter-Integrated Circuit (I2C) Bus. More generally, various aspects of the present disclosure are directed to enabling rapid transactions over a speed limited bus.
2. Description of Related Technology
The Inter-Integrated Circuit (I2C) bus technology is a multi-master, multi-slave, single-ended serial bus technology which is commonly used in consumer electronics devices. The I2C bus uses two bi-directional open-drain lines to transact serial data (SDA), and serial clock (SCL). Traditionally, the I2C bus is most commonly used within consumer applications as an interconnect bus technology for different integrated circuits (ICs) which may each independently arbitrate for control of the bus and thereafter transact data.
As a brief aside, extant I2C operation is based on a master-slave (master-peripheral) protocol; a node arbitrates to become master of the bus, and thereafter can write to any of the other nodes. Once the master node relinquishes control of the I2C bus, another node can arbitrate to become a master. In this manner, any node can master the bus, and any node can be addressed as a slave. It is worth noting that the I2C bus uses open-drain drivers. Open-drain technology allows any node to assert a logic low (by driving the signal to GND), but the bus must float in order to signal a logic high (e.g., via pull up resistors to Vdd). Since open-drain nodes can only drive GND, the bus does not experience drive conflicts (where one node drives logic low and another node drives a logic high).
While the I2C bus has wide-spread adoption within embedded circuit solutions and provides significant benefits, those of ordinary skill in the related arts will readily appreciate that the arbitration process in combination with the open-drain technology of the I2C bus is relatively slow. Moreover, certain types of applications may have repetitive (or relatively “fixed”) tasks which are periodically executed. In these instances, the flexibility of I2C technology is less important, and the overall transaction speed is a significant limitation.
Accordingly, improved methods and apparatus are needed for providing rapid transaction capabilities via the I2C bus. More generally, solutions are needed for enabling rapid transactions over a speed limited bus.